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74VHCT373A
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING
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HIGH SPEED: tPD = 6.4 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (Max.)
M (Micro Package)
T (TSSOP Package)
ORDER CODES : 74VHCT373AM 74VHCT373AT (OE). While the LE input is held at a high level, the Q outputs will follow the data inputs precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
DESCRIPTION The 74VHCT373A is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. This 8 bit D-Type latch is controlled by a latch enable input (LE) and an output enable input
PIN CONNECTION AND IEC LOGIC SYMBOLS
November 1999
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INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL OE Q0 to Q7 NAME AND FUNCT ION 3 State Output Enable Input (Active LOW) 3 State Outputs
D0 to D7
Data Inputs
LE GND VCC
Latch Enable Input Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUTS OE H L L L LE X L H H D X X L H OUT PUTS Q Z NO CHANGE * L H
X:DON'T CARE Z: HIGH IMPEDANCE *: Q OUTPUTSARE LATCHED AT THE TIME WHEN THE LEINPUT ISTAKEN LOW LOGIC LEVEL.
LOGIC DIAGRAM
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ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage (see note 1) DC Output Voltage (see note 2) DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 20 25 50 -65 to +150 300 Unit V V V V mA mA mA mA
o o
ICC or IGND DC VCC or Ground Current
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. 1) Output in OFF State 2) High or Low State
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO VO Top dt/dv Supply Voltage Input Voltage Output Voltage (see note 1) Output Voltage (see note 2) Operating Temperature Input Rise and Fall Time (see note 3) (V CC = 5.0 0.5V) Parameter Valu e 4.5 to 5.5 0 to 5.5 0 to 5.5 0 to VCC -40 to +85 0 to 20 Unit V V V V
o
C
ns/V
1) Output in OFF State 2) High or Low State 3)VIN from0.8V to 2 V
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DC SPECIFICATIONS
Symb ol Parameter T est Cond ition s V CC (V) VIH VIL VOH VOL IOZ High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current Additional Worst Case Supply Current Output Leakage Current 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 4.5 to 5.5 I O =-50 A IO=-8 mA I O=50 A IO=8 mA VI = VIH or VIL VO = 0V to 5.5V VI = 5.5V or GND VI = VCC or GND One Input at 3.4V, other input at VCC or GND VOUT = 5.5V 4.4 3.94 0.0 0.1 0.36 0.25 4.5 Min. 2 0.8 4.4 3.8 0.1 0.44 2.5 Typ . Value T A = 25 o C Max. -40 to 85 o C Min . 2 0.8 Max. V V Un it
V V A
II ICC ICC
0 to 5.5 5.5 5.5
0.1 4 1.35
1.0 40 1.5
A A mA
IOPD
0
0.5
5.0
A
AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns)
Symb ol Parameter V CC (V) tPLH tPHL tPLH tPHL tPZL tPZH tPLZ tPHZ tw ts th tOSLH tOSHL Propagation Delay Time LE to Q Propagation Delay Time D to Q Output EnableTime Output Disable Time Pulse Width (LE) HIGH Setup Time D to LE HIGH or LOW Hold Time D toLE HIGH or LOW Output to Output Skew Time (note 1) Test Co ndition CL (pF ) 15 50 15 50 15 50 50 R L = 1K R L = 1K 6.5 1.5 3.5 50 1.0 Value T A = 25 o C Min. Typ . Max. 5.4 6.0 6.4 7.1 6.2 6.9 6.7 12.3 13.3 8.5 9.5 10.9 11.9 11.2 Un it -40 to 85 o C Min . Max. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 8..5 1.5 3.5 1.0 13.5 14.5 9.5 10.5 12.5 13.5 12.0 ns ns ns ns ns ns ns ns
5.0 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*)
(*)
(*) Voltage range is 5V 0.5V Note 1: Parameter guaranteed by design. tsoLH = |tpLHm- tpLHn|, tsoHL = |tpHLm - tpHLn|
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CAPACITIVE CHARACTERISTICS
Symb ol Parameter T est Cond ition s Min. C IN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) Typ . 4 9 14 Value T A = 25 o C Max. 10 -40 to 85 o C Min . Max. 10 pF pF pF Un it
1) CPD isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD * VCC * fIN + ICC/8 (per Latch)
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol Parameter T est Cond ition s V CC (V) VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 5.0 -0.9 5.0 5.0 C L = 50 pF 2.0 0.8
o
Value T A = 25 C Min. Typ . 0.6 -0.6 Max. 0.9 -40 to 85 C Min . Max.
o
Un it
V
1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n -1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to3.0V. Inputs under test switching: 3.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.
TEST CIRCUIT
T EST tPLH , tPHL tPZL , tPLZ tPZH , tPHZ
CL = 15/50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 1K orequivalent RT = ZOUT of pulse generator (typically 50)
SW IT CH Open VCC GND
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WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
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WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 3: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
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SO-20 MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.40 0.50 12.60 10.00 1.27 11.43 7.60 1.27 0.75 8 (max.) 0.291 0.19 13.00 10.65 0.35 0.23 0.50 45 (typ.) 0.496 0.393 0.050 0.450 0.299 0.050 0.029 0.512 0.419 0.10 mm TYP. MAX. 2.65 0.20 2.45 0.49 0.32 0.013 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.007 0.096 0.019 0.012
P013L
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TSSOP20 MECHANICAL DATA
mm MIN. A A1 A2 b c D E E1 e K L 0o 0.50 0.05 0.85 0.19 0.09 6.4 6.25 4.3 6.5 6.4 4.4 0.65 BSC 4o 0.60 8o 0.70 0o 0.020 0.10 0.9 TYP. MAX. 1.1 0.15 0.95 0.30 0.2 6.6 6.5 4.48 0.002 0.335 0.0075 0.0035 0.252 0.246 0.169 0.256 0.252 0.173 0.0256 BSC 4o 0.024 8o 0.028 0.004 0.354 MIN. inch TYP. MAX. 0.433 0.006 0.374 0.0118 0.0079 0.260 0.256 0.176
DIM.
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
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Information furnished is believed to be accurate and reliable. However, STMicroelectronic s assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com .
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